The present invention relates generally to a level shift circuit and more particularly to a level shift circuit that may provide an interface between internal circuits of a semiconductor integrated circuit and external circuits and/or between internal circuits of a semiconductor integrated circuit operating from different power supply potentials.
A level shift circuit can be used as an interface between circuits operating at different power supply voltages. A level shifter can receive a signal having a first power supply level and provides a signal having a second power supply level. As manufacturing processes become finer and/or lower power consumption becomes desirable, internal circuits of a semiconductor integrated circuit (such as a large scale integrated circuitxe2x80x94LSI) are reduced. However, a semiconductor integrated circuit can be included in a system operating at a higher power supply voltage. In this case, an interface circuit is required to provide an interface between external signals and internal signals having different voltage swings. In systems in which the system voltage has not been stepped down, the difference between the system power supply potential and the power supply potential for internal circuits on a semiconductor integrated circuit can be great. Because different systems may operate at different power supply potentials, the interface circuit needs to operate over a wide range. However, sizing of devices in a level shift circuit may be different for optimal performance at different power supply potentials. Due to the need to provide an interface circuit that operates over such a wide range of power supply potentials, design and development time may be increased.
Also, in order to provide a LSI that can have low power consumption capabilities and/or high speed capabilities as required by the system, a method has been established in which an LSI is operated by changing internal and/or external poser supply voltages during usage as necessary. This has led to a demand that a wide range of internal and external voltages being supported with a single level shift circuit while maintaining operating characteristics (such as delay time). Additionally, in recent years, a complementary signal output has been adopted or a method with which data is sampled/provided by detecting a rising and a falling edge of a clock signal. As a result, in a level shift circuit, it has become increasingly important that differences in delay times occurring when an output signal rises and a delay time when an output signal falls be reduced or eliminated.
Referring to FIG. 9, a circuit schematic diagram of a conventional level shift circuit is set forth and given the general reference character 101.
Conventional level shift circuit 101 includes inverters (111 and 112) and a level shift flip-flop portion 113. Level shift circuit 101 is supplied with power supply voltages (VDD1 and VDD2), where power supply voltage VDD1xe2x89xa6power supply voltage VDD2. Inverter 111 is constructed from n-channel transistor N101 and p-channel transistor P101. Inverter 112 is constructed from n-channel transistor N102 and p-channel transistor P102. Level shifter flip-flop portion 113 is constructed from n-channel transistors (N103 and N104) and p-channel transistors (P103 and P104).
In level shift circuit 101, the drive capabilities of p-channel transistors (P103 and P104) are set to be small and the drive capabilities of n-channel transistors (N103 and N104) are set to be large in order to support a wide range of differences between internal and external voltages. In order to support such a wide range of differences, a large difference between driving capabilities are maintained in this manner. However, because of the drive capability differences, a large difference between an input-output delay time (delay time between an input signal at terminal A and an output signal at terminal Y) occurs between an input-output delay time for a rising edge signal and a falling edge signal.
In order to reduce such a difference between input-output delay times, JP 2001-068991 A and JP 11-239051 A disclose level shift circuits where an output terminal of the level shift circuit is provided with a pull-up circuit.
Referring now to FIG. 10, a circuit schematic diagram of a conventional level shift circuit as disclosed in JP 2001-068991 A is set forth. The conventional level shift circuit of FIG. 10 includes a level shift portion 101 (identical to level shift circuit 101 of FIG. 9) and a pull-up portion 102. Pull-up portion 102 includes p-channel transistors (P121 and P122) and inverters (121 and 122).
Referring now to FIG. 11, a circuit schematic diagram of a conventional level shift circuit as disclosed in JP 2001-239051 A is set forth. The conventional level shift circuit of FIG. 11 includes a level shift portion 101 (identical to level shift circuit 101 of FIG. 9) and a pull-up portion 102a. Pull-up portion 102a includes p-channel transistors (P123 and P124) and inverters (123 and 124).
In conventional level shift circuits illustrated in FIGS. 10 and 11, by providing pull-up portions (102 and 102a), it may be possible to improve an input-output delay time in the case of a rising output signal.
However, the conventional level shift circuit disclosed in JP 2001-068991 A (FIG. 10) has a drawback in that if a potential difference between power supply voltage VDD1 and power supply voltage VDD2 is increased, the effect of pull-up portion 102 is reduced and the difference between input-output delay times are increased. Also, the conventional level shift circuit disclosed in JP 11-239051 A (FIG. 11) has a drawback that if the power supply voltage VDD2 fluctuates, the pull-up capabilities of pull-up portion 102a also varies which causes the difference between input-output delay times to vary.
Also, in conventional level shift portion 101, the delay time difference tends to vary in accordance with the fluctuations of power supply voltages. When power supply voltage VDD1 fluctuates the gate to source voltage (Vgs) of n-channel transistors (N103 and N104) vary and the drive capabilities of n-channel transistors (N103 and N104) vary accordingly. Consequently, a delay time occurring when the potential of a terminal (114 or 115) switches from a logic high level to a logic low level varies. On the other hand, when power supply voltage VDD2 fluctuates, the gate to source voltages (Vgs) of p-channel transistors (P103 and P104) vary and the drive capabilities of p-channel transistors (P103 and P104) vary accordingly. Consequently, a delay time occurring when the potential of terminal (114 or 115) switches from a logic low level to a logic high level varies.
For the reasons described above, an input-output delay time for both a rising output signal and a falling output signal can vary in accordance with variations in power supply voltages (VDD1 and VDD2). Also, the difference between the delay times between a rising output signal and a falling output signal varies in accordance with variations in power supply voltages (VDD1 and VDD2). As a result, conventional level shift circuits have a drawback in that when an internal power supply voltage or an external power supply voltage fluctuates, it may be difficult to reduce a difference between an input-output delay time between a rising output signal and a falling output signal.
In view of the above discussion, it would be desirable to provide level shift circuit that may be capable of improving delay time characteristics and reducing a difference between delay times even if a power supply voltage fluctuates over a wide range.
According to the present embodiments, a level shift circuit that may have reduced input-output timing differences is disclosed. A level shift circuit may include a level shift portion and a signal selection portion. A level shift portion may receive an input signal at an input terminal operating at a first voltage and may provide complementary signals at terminals operating at a second voltage. A signal selection circuit may include a first signal propagation path for timing an output signal at an output terminal based on a signal at one terminal and a second signal propagation path for timing an output signal at an output terminal based on a signal at another terminal. The first signal propagation path may be selected when a signal at one terminal transitions from high to low and the second signal propagation path may be selected when a signal at another terminal transitions from high to low. In this way, a delay difference caused by differences in timings of a rising edge and a falling edge of a signal may be reduced.
According to one aspect of the embodiments, a level shift circuit may be supplied with a first power supply potential, a second power supply potential, and a reference potential and may convert an input signal having a first potential swing to an output signal having a second potential swing. The first potential swing may be essentially a potential difference between the first power supply potential and the reference potential. The second potential swing may be essentially a potential difference between the second power supply potential and the reference potential. The level shift circuit may include a level shift portion and a signal selection portion. The level shift portion may receive the input signal and may generate first and second signals. The first and second signals may have complementary logic levels and may have the second potential swing. The signal selection portion may receive the first and second signals and may provide the output signal. The output signal may have a transition based on the first signal when the first signal transitions from a high logic level to a low logic level and based on the second signal when the second signal transitions from the high logic level to the low logic level.
According to another aspect of the embodiments, the level shift portion may include a first node, a second node, a first inverter, a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor. The first signal may be provided at the first node and the second signal may be provided at the second node. The first inverter may be supplied with the first power supply potential and the reference potential. The first inverter may receive the input signal and may generate an inverted signal having the first potential swing. The first p-channel transistor may have a source connected to the second power supply potential, a gate connected to the second node, and a drain connected to the first node. The second p-channel transistor may have a source connected to the second power supply potential, a gate connected to the first node, and a drain connected to the second node. The first n-channel transistor may have a drain connected to the first node, a gate connected to receive the inverted signal, and a source connected to the reference potential. The second n-channel transistor may have a drain connected to the second node, a gate connected to receive the input signal, and a source connected to the reference potential.
According to another aspect of the embodiments, the level shift portion may include a first node, a second node, a first inverter, a first p-channel transistor, a second p-channel transistor, a third p-channel transistor, a fourth p-channel transistor, a first n-channel transistor, and a second n-channel transistor. The first signal may be provided at the first node and the second signal may be provided at the second node. The first inverter may be supplied with the first power supply potential and the reference potential. The first inverter may receive the input signal and may generate an inverted signal having the first potential swing. The first p-channel transistor may have a source connected to the second power supply potential, a gate connected to the third node, and a drain connected to a fourth node. The second p-channel transistor may have a source connected to the second power supply potential, a gate connected to the fourth node, and a drain connected to the third node. The third p-channel transistor may have a source connected to the third node, a gate connected to a third power supply potential, and a source connected to the first node. The fourth p-channel transistor may have a source connected to the fourth node, a gate connected to a third power supply potential, and a source connected to the second node. The first n-channel transistor may have a drain connected to the first node, a gate connected to receive the inverted signal, and a source connected to the reference potential. The second n-channel transistor may have a drain connected to the second node, a gate connected to receive the input signal, and a source connected to the reference potential.
According to another aspect of the embodiments, the signal selection portion may include an output terminal, a first inverter, a first clocked inverter, a second clocked inverter, and a logic circuit. The output signal may be received at the output terminal. The first inverter may be supplied with the second power supply potential and may have a first inverter input and a first inverter output. The first inverter input may receive the first signal. The first clocked inverter may be supplied with the second power supply potential and may receive the first inverter output at a first clocked inverter input and a first control signal at a first clocked inverter control terminal. The first clocked inverter may have a first clocked inverter output connected to the output terminal. The second clocked inverter may be supplied with the second power supply potential and may receive the second signal at a second clocked inverter input and the first control signal at a second clocked inverter control terminal. The second clocked inverter may have a second clocked inverter output connected to the output terminal. The logic circuit may generate the first control signal. The first clocked inverter may be in an operation state when the first signal has a high logic level and the second clocked inverter may be placed in the operation state a predetermined time after the first signal transitions to the low logic level. The second clocked inverter may be in an operation state when the second signal has a high logic level and the first clocked inverter may be placed in the operation state a predetermined time after the second signal transitions to the low logic level.
According to another aspect of the embodiments, the first clocked inverter may include a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor. The second clocked inverter may include a third p-channel transistor, a fourth p-channel transistor, a third n-channel transistor, and a fourth n-channel transistor. The first p-channel transistor may have a source connected to the second power supply potential, a gate connected to receive the first control signal, and a drain connected to a source of the second p-channel transistor. The second p-channel transistor may have a gate connected to the first inverter output and a drain connected to the output terminal. The first n-channel transistor may have a source connected to the output terminal, a gate connected to the first inverter output, and a source connected to a drain of the second n-channel transistor. The second n-channel transistor may have a gate connected to a second control signal and a source connected to the reference potential. The third p-channel transistor may have a source connected to the second power supply potential, a gate connected to receive the second control signal, and a drain connected to a source of the fourth p-channel transistor. The fourth p-channel transistor may have a gate connected to receive the second signal and a drain connected to the output terminal. The third n-channel transistor may have a source connected to the output terminal, a gate connected to receive the second signal, and a source connected to a drain of the fourth n-channel transistor. The fourth n-channel transistor may have a gate connected to the first control signal and a source connected to the reference potential.
According to another aspect of the embodiments, the second signal is received at a second signal terminal. The signal selection portion may include a first inverter, a first transfer gate, and a second transfer gate. The first inverter may be supplied with the second power supply potential and may have a first inverter input and a first inverter output. The first inverter input may receive the first signal. The first transfer gate may be disposed between the first inverter output and the output terminal and may have a first transfer gate control terminal coupled to receive a first control signal. The second transfer gate may be disposed between the second signal terminal and the output terminal and may have a second transfer gate control terminal coupled to receive a first control signal.
According to another aspect of the embodiments, the first transfer gate includes a first p-channel transistor and a first n-channel transistor and the second transfer gate includes a second p-channel transistor and a second n-channel transistor. The first p-channel transistor may have a first source/drain terminal connected to receive the first inverter output, a second source/drain terminal connected to the output terminal, and a gate connected to receive the first control signal. The first n-channel transistor may have a first source/drain terminal connected to receive the first inverter output, a second source/drain terminal connected to the output terminal, and a gate connected to receive a second control signal. The second p-channel transistor may have a first source/drain terminal connected to receive the second signal, a second source/drain terminal connected to the output terminal, and a gate connected to receive the second control signal. The third n-channel transistor may have a first source/drain terminal connected to receive the second signal, a second source/drain terminal connected to the output terminal, and a gate connected to receive the first control signal.
According to another aspect of the embodiments, a level shift circuit may include a level shift portion and a signal selection portion. The level shift portion may receive an input signal and may generate first and second signals. The signal selection portion may include a first signal path circuit and a second signal path circuit. The first signal path circuit may receive the first signal and provide an output signal in response to the first signal transitioning from a first logic level to a second logic level. The second signal path circuit may receive the second signal and provide an output signal in response to the second signal transitioning from the first logic level to the second logic level.
According to another aspect of the embodiments, the level shift circuit may include a control circuit. The control circuit may receive the output signal and provide a control signal to the first signal path circuit and the second signal path circuit. The first signal path circuit may be enabled in response to the output signal having a first output signal logic level and the second signal path may be enabled in response to the output signal having a second output signal logic level.
According to another aspect of the embodiments, the level shift circuit may include a control circuit. The control circuit may receive the first signal and the second signal and provide a control signal to the first signal path circuit and the second signal path circuit. The first signal path may be enabled in response to the first signal having the first logic level and the second signal having the second logic level. The second signal path may be enabled in response to the second signal having the first logic level and the first signal having the second logic level.
According to another aspect of the embodiments, the control circuit may include a flip-flop coupled to receive the first signal and the second signal.
According to another aspect of the embodiments, the first signal may have a first transition time for the first logic level to the second logic level transition and a second transition time for the second logic level to the first logic level transition. The second transition time may be greater than the first transition time.
According to another aspect of the embodiments, the first signal path circuit may include a first clocked inverter and the second signal path circuit may include a second clocked inverter.
According to another aspect of the embodiments, the first signal path circuit may include a first transfer gate and the second signal path circuit may include a second transfer gate.
According to another aspect of the embodiments, a level shift circuit may include a level shift portion and a signal selection portion. The level shift portion may receive an input signal having a first voltage swing and may generate first and second signals having a second voltage swing. The second voltage swing may be greater than the first voltage swing. The second selection portion may include a first signal path circuit and a second signal path circuit. The first signal path circuit may receive the first signal and provide an output signal in response to the first signal transitioning from a first logic level to a second logic level. The second signal path circuit may receive the second signal and provide an output signal in response to the second signal transitioning from the first logic level to the second logic level.
According to another aspect of the embodiments, the level shift circuit may include a control circuit. The control circuit may receive the output signal and provide a signal path control signal. The first signal path circuit may include a first clocked inverter connected to receive the signal path control signal. The second signal path circuit may include a second clocked inverter connected to receive the signal path control signal.
According to another aspect of the embodiments, the level shift circuit may include a control circuit. The control circuit may receive the output signal and provide a signal path control signal. The first signal path circuit may include a first transfer gate connected to receive the signal path control signal. The second signal path circuit may include a second transfer gate connected to receive the signal path control signal.
According to another aspect of the embodiments, the level shift circuit may include a control circuit. The control circuit may receive the first signal and the second signal and provide a signal path control signal. The first signal path circuit may include a first clocked inverter connected to receive the signal path control signal. The second signal path circuit may include a second clocked inverter connected to receive the signal path control signal.
According to another aspect of the embodiments, the level shift circuit may include a control circuit. The control circuit may receive the first signal and the second signal and provide a signal path control signal. The first signal path circuit may include a first transfer gate connected to receive the signal path control signal. The second signal path circuit may include a second transfer gate connected to receive the signal path control signal.
According to another aspect of the embodiments, the level shift circuit may include a control circuit. The control circuit may provide a control signal to the first signal path circuit and the second signal path circuit. The output signal may make a first logic transition in response to the first signal transitioning from a first logic level to a second logic level. The control signal may enable the second signal path circuit and disable the first signal path circuit after the first transition. The output signal may make a second logic transition in response to the second signal transitioning from the first logic level to the second logic level. The control signal may enable the first signal path circuit and disable the second signal path circuit after the second transition.